Forum Discussion
Altera_Forum
Honored Contributor
7 years agoYeah thats what I figured, I just have 80Mbits per second coming into the FPGA and need to be sending 80Mbits per second from the FPGA to the HPS, hopefully I can achieve that with this implementation of the FPGA-2-HPS bridge. Now I just need to work on the verilog logic to set up a loop to break up that 37Kbit and repeatedly write it to the bridge.