data changed from RAM output port

I have a design using 10AX057N4F40E3SG compiled with Quartus Prime Standard 17.1, these is a error with simple dual-port RAM，that is data changed in the RAM when data is read out。the Dual-Port RAM is configured as 2048-depth and 32-bit word width. I tested the dual-port RAM with a serial of ascending data at the write port , and then read those data out at the read port, and find somewhere data changed. As showed in the attachment, the expecting data should be 'Bxxx'，but the read-out data actually is '9xxx'，bit25 changed from 1 to 0. The logic utilization is 74% in ALMs，and the total memory bits used is 52% for the whole design. I wonder why this happened ,and how to solve this problem?