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User1584607963412451's avatar
User1584607963412451
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Damaged/Defective part to send for FA

Hi Team

We have received RMA for part#A1822-5790 with MPN: 10M08DAU324I7G. Currently we would like to seek for your help to send this damaged/defective FPGA to Intel for failure analysis. We already check on the X-ray images of U114 BGA and it is clean. Please find attached the image of physical for your checking.

Due to urgency, seek for your help to revert to us at soonest possible.

Thank you & Regards

CheeHeng Ng

5 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi CheeHeng Ng,

    Thanks for performing X-ray test.

    1. Can you elaborate more on what's the failure symptom ? Kindly fill up attached "failure description form" template to help me understand your issue better.
    2. Also may I know what else of debugging that Jabil has performed to isolate this is potential defective FPGA issue ?
      • Like have you perform unit swap test ? replace another good unit on failure board then test passed ? solder bad unit to another board and test fail as failure symptom follow defective unit.

    Thanks.

    Regards,

    dlim

      • Deshi_Intel's avatar
        Deshi_Intel
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        Hi,

        Thanks for clarifying the failure symbol.

        Now I understand the failure is regarding issue in detecting FPGA itself.

        • I presume this is abnormal case with low failure rate and not related to potential manufacturing process itself, right ?
        • Max 10 FPGA contains internal flash inside the device itself. Sometime the FPGA detection issue is due to user program corrupted image to the flash causing whole Max10 can't be detected anymore. Has Jabil work with your designer team to delete the flash content to debug this issue ?

        On a side note, pls help to file up attached DPR form to help me understand the issue background and debug that Jabil has done so far (only fill up second FPGA-CPLD sheet).

        • So take note that you confused on FPGA MPN, Lot number, Date code and trace code marking info earlier. You can refer to "Altera" pic diagram that explained on how to read the device marking info accordingly

        Thanks.

        Regards,

        dlim

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,


    I am setting this case to closure since I have not hear back from you after I provided feedback in Sept 3.


    Feel free to post new forum thread again if you would like to resume support discussion in future.


    Thanks.


    Regards,

    dlim