Altera_Forum
Honored Contributor
10 years agoD type flip flop with out a reset pin
I'm trying to implement a flip flop and i don't want it to have a reset pin. I just want 2 inputs D and CK and two outputs Q and notQ my VHDL code is shown below.
--- Quote Start --- library IEEE;use IEEE.STD_LOGIC_1164.all; -- D type flip flop Entity flipflop is port ( D, CK : in std_logic; Q, notQ: out std_logic ); end entity; architecture random of flipflop is signal f1,f2,f3,f4,f5: std_logic ; begin f1 <= D nand CK; f2 <= not D; f3 <= ck nand f2; f4 <= f1 nand f5; f5 <= f3 nand f5 ; NotQ <= f5 ; Q <= f4; end random; --- Quote End --- My simulation file is attached. Can someone tell me have i done everything correctly? Is my simulation file correct and is my code correct too? Simulation file is in the pdf attachment