D type flip flop with out a reset pin

If it seems correct, then good.

But you would never describe a flip-flop like this in an FPGA for several resons:

1. An FPGA has no gates, so has to build the design from LUTs

2. Because it is all gates, it is going to be affected by PVT (process, voltage, temperature) in that timing will change depending on PVT.

3. There are dedicated flip-flops in the FPGA fabric.

From the code it looks like you coded from a text-book diagram of a flip-flop. No one would ever do this in reality.

A D flip-flop used in real life in VHDL:

entity flipflop is
  port (
  D   : in  std_logic;
  CK  : in  std_logic;
  Q   : out std_logic;
  notQ: out std_logic );
end entity;
architecture rtl of flipflop is
begin
  process(ck)
  begin
    if rising_edge(ck) then
      Q    <= D;
      notQ <= not D
    end if;
  end process;
end architecture rtl;

Also note - no one would ever make such a simple entity. An entity would usually contain code that synthesised to many (possibly 1000s) of flipflops.