D flip flop trouble

The sim may have worked fine since you initialized the registers to 1. Registers initialize to 0 in hardware.

A circuit like this should really be clocked. Here's one I like that I've been using that uses a counter. button_qual high indicates a debounced button press:

module button_debounce(

input wire clock,

input wire button,

output reg button_qual = 1'b0

);

reg [19:0] button_count = 20'h00000;

reg [2:0] button_reg = 3'b000;

reg [1:0] button_state = 2'b00;

always @ (posedge clock)

begin

button_reg <= {button_reg[1:0],button};

case (button_state)

2'b00: begin

button_qual <= 1'b0;

button_count <= 8'h00;

if (button_reg[2])

button_state <= 2'b01;

else

button_state <= 2'b00;

end

2'b01: begin

button_qual <= 1'b1;

button_count <= button_count + 1'b1;

button_state <= 2'b10;

end

2'b10: begin

button_qual <= 1'b1;

button_count <= button_count + 1'b1;

button_state <= button_count[4] ? 2'b11 : 2'b10;

end

2'b11: begin

button_qual <= 1'b0;

button_count <= button_count + 1'b1;

button_state <= button_count[19] ? 2'b00 : 2'b11;

end

endcase

end

endmodule