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Honored Contributor
Honored ContributorCylone II FPGA Clock input
In my design ，the FPGA uses single-end clock input, the clock is 40MHz signal ,3.3 Vpp and 6.6Vpp , the Voltage is -1.55~+1.55V and -3.3~+3.3V, but the FPGA I/O Voltage :-0.8V~4.1V. My ...
Altera_ForumHonored Contributor
Honored ContributorYou can limit this signal by TVS diodes. Or you can use signal transformer and en example 74HC schmitt trigger.
