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Honored ContributorCylone II FPGA Clock input
In my design ，the FPGA uses single-end clock input, the clock is 40MHz signal ,3.3 Vpp and 6.6Vpp , the Voltage is -1.55~+1.55V and -3.3~+3.3V, but the FPGA I/O Voltage :-0.8V~4.1V. My ...
Altera_ForumHonored Contributor
Honored ContributorFvM： thank you! You understand my questions. I have a usual 3.3V clock oscillator connected to the FPGA clock input, and at the same time ,I have another external interface to supply a clock input ,the source is -3.3V~3.V 40MHz signal,+3.3V is not bigger than specification(+4.1V), -3.3V is less than -0.8V too much ,I don't know whether it will cause some problem？
