cycloneIV GX use 3.0Gbps data rate.error:reserved_gnd_ac5 is too close to lvds IO

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what can i do ?

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Generally you do the pin assignments before board layout to ensure you have met these placement rules.

In the case of a development kit where you do not have a choice, you make a judgement call and override the rule using an I/O toggle rate assignment.

I think this is the constraint you need (if its not, its something like this ...)

http://quartushelp.altera.com/14.0/mergedprojects/logicops/logicops/def_toggle_rate.htm

Cheers,

Dave

Hi, this error message is because you are placing the non-differential io standard too close the differential io standard.

you can refer to the following link as reference

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05052003_3407.html