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Altera_Forum
Honored Contributor
Honored ContributorcycloneIV GX use 3.0Gbps data rate.error:reserved_gnd_ac5 is too close to lvds IO
hi
device is EP4CGX110DF23. refclk is connect REFCLK[0] of pin T9.altgx data rate is set to 3000Mbps. Set pin AC5,AD4,AB5,etc to connect GND. quaturs report a error:non-differential I/O pin ' ref-clk-reserved_gnd_AC5' in pin location AC5 is too close to pad 51 of differential I/O pin 'Lvds[4]' in pin location AE1 -- pads must be separeted by a minimum of 5 pads. what can i do ?2 Replies
Altera_Forum--- Quote Start --- what can i do ? --- Quote End --- Generally you do the pin assignments before board layout to ensure you have met these placement rules. In the case of a development kit where you do not have a choice, you make a judgement call and override the rule using an I/O toggle rate assignment. I think this is the constraint you need (if its not, its something like this ...) http://quartushelp.altera.com/14.0/mergedprojects/logicops/logicops/def_toggle_rate.htm Cheers, Dave- Altera_Forum
Hi, this error message is because you are placing the non-differential io standard too close the differential io standard.
you can refer to the following link as reference https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05052003_3407.html
