CycloneIV adder behavior

Hi everyone,

I have a snippet of code that adds.

    logic bitCount;
    always_ff @ (negedge sck, posedge cs)
    begin
        if (cs)
            bitCount <= 4'b0000;
        else
        begin
            bitCount <= bitCount + 4'b0001;
        end
    end

This code returns the desired value by the next clock cycle. However, if I increase the bit width of bitCount above 4 bits, the sum does not return by the next clock cycle but the clock cycle afterwards. Can someone explain whys this is? Does this relate to how the add function is implemented?