cycloneIII configuration problems

Question

hello

recently i am testing my board with a cycloneIII device. its configuration device is epc16. i can successfully program fpga, but fpga can not work fine. although my vhdl program is a very simple program. for example, i set an output with level '0'. i think the program in epc16 is not really loaded in fpga. i wonder if in AS configuration schehme i should connect a 25 ohm resistance between Serial Configuration Device DATA and cycloneiii device DATA[0] which is noted in figure 10-3 of cycloneiii handle book.

this is my first thread in altera forum, please help me.

my native language is not english, i so sorry that in this article i may make some mistake.

Thank you much,

kevin

altera_forum · Answer

this 25ohm resistor is a must have on cyclone III between the DATA output of your EPCS and the DATA[0] of the FPGA. i have seen this resistor in the altera docs about AS configuration and my FAE strongly advised me to use it. You must place this resistor as close to the data output pin of your EPC(S) as possible. but this is also mentioned in the altera docs.

the cyclone III devices need that you take care about the external signals especially if you use 3,3V IO.

with all these "must look after" in cyclone III it took me longer for the designs as for cyclone II, but now they run fine.

altera_forum · Answer

I guess, you mean EPCs16 rather than EPC16? You didn't tell your exact hardware configuration, e.g. according to which handbook's schematic. You also didn't tell, if programming and verify of AS device proceeded correct in Quartus programmer. I think, the said 25 ohms resistor only matters, if there is a least one inch distance between FPGA and AS memory, but there are many possible hardware faults apart.

altera_forum · Answer

thank you very much

my configuration device is epcs16. and hardware is byteplasterII. i can program FPGA successfully but it did not seems work fine. i program the same code to starixII it can work fine. here is my test code:

library ieee;

use ieee.std_logic_1164.all;

entity test is

port

(

clk : in std_logic;

clk_out : out std_logic;

A0 : out std_logic;

A1 : out std_logic

);

end entity;

architecture rtl of test is

begin

A0 <= '0';

A1 <= '0';

clk_out <= clk;

end rtl;

altera_forum · Answer

--- Quote Start ---

this 25ohm resistor is a must have on cyclone III between the DATA output of your EPCS and the DATA[0] of the FPGA. i have seen this resistor in the altera docs about AS configuration and my FAE strongly advised me to use it. You must place this resistor as close to the data output pin of your EPC(S) as possible. but this is also mentioned in the altera docs.

the cyclone III devices need that you take care about the external signals especially if you use 3,3V IO.

with all these "must look after" in cyclone III it took me longer for the designs as for cyclone II, but now they run fine.

--- Quote End ---

michael, thank you very much

altera_forum · Answer

so you should have 2 pins that are forced to be 0 and another one is toggling. this is theory and how is it in real life on your fpga ? what is working and what is not working ?

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cycloneIII configuration problems

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