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Altera_Forum's avatar
Altera_Forum
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16 years ago

Cyclone3 Power Up level doesn't work

A design with an EP3C40F324I7 has the pin U18 as an registered output.

This pin is used to control another dcdc's nSHDN (Shutdown negativ logic)

The fpga is configured via epcs.

this dcdc is under control of a custom ip and is only powered up when needed as this is a battery powered design.

During power up, as soon as the voltages are stable the pin goes to high and the dcdc starts. the fpga gets its configuration from the epcs. when the configuration is done the pin goes to low as this is the default level of this pin.

i want that this pin is low after power up until the custom ip sets it to high to enable the dcdc. this is done as soon as the fpga is in user mode but not during configuration.

The pin U18 is a Column IO and the PLL4_CLKOUTp.

Quartus has an option Power Up Level and it is used as

set_location_assignment PIN_U18 -to 3VEnable

set_instance_assignment -name POWER_UP_LEVEL LOW -to 3VEnable

But this does not help.

Quartus reports

Warning: Pin "3VEnable" has no register for Power-Up Level option

but this is my verilog code sniped

reg Enable_3V;

always @ ( posedge gls_clk or negedge gls_reset_n )

if ( !gls_reset_n )

Enable_3V <= 1'b0;

the register Enable_3V goes to top level and there it is connected to output pin 3VEnable

if i am not wrong, then this is a register but why does quartus think it is not a register ?

But more important how can i force my pin to low during power up.

please notice that there is a pull down on that pin.

it is a resistor devider 100k + 560k with a 47nF cap in parallel to the 560k. this will give ~2,5v maximum and a smooth softstart to reduce the startup durrent.

any ideas ?

thanks in advance.

Michael

EDIT : it is Pin U18

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You can expect about 100 ohm output resistance at LVTTL3.3V 4 mA respectively 50 ohm at 8 mA. Additionally, the 4 mA setting causes current limit at about 18 mA.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I appologize. I initially misunderstood and thought you were trying to power-up high. Not low.

    Jake

    --- Quote Start ---

    @Daixiwen

    @ Jake

    i tried different ways

    //verilog 1995

    reg Enable_3V /* synthesis altera_attribute = "-name POWER_UP_LEVEL LOW" */;

    // Verilog 2001

    (* altera_attribute = "-name POWER_UP_LEVEL LOW" *) reg Enable_3V;

    as well as

    reg Enable_3V = 1'b0;

    but none of them works.

    between power on and until the fpga starts to work in user mode the pin is 1

    as soon as the user mode is reached, this pin goes to 0

    so it seems that it is realy impossible ...

    i can't go to 2k pull down as this will disable the soft start function of the dcdc

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I just wonder is 3VEnable and Enable_3V connected? You have the pin as 3VEnable, but the reg as Enable_3V. In this regard, the synthesis tool does not know you have a register at the output pin.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    @ gambit

    in my first posting i mentioned "the register Enable_3V goes to top level and there it is connected to output pin 3VEnable"

    @ jake

    no matter if low or high, you gave me a realy good hint and i must find some time to read those manuals again. unfortunately it seems that there won't be a working solution with parts available in 0402, the startup current is too high so i must decide between no running dcdc between startupwith a too high power up current in normal operating or a short dcdc start but a smal current ramp ....