Cyclone3 Power Up level doesn't work

I appologize. I initially misunderstood and thought you were trying to power-up high. Not low.

Jake

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@Daixiwen

@ Jake

i tried different ways

//verilog 1995

reg Enable_3V /* synthesis altera_attribute = "-name POWER_UP_LEVEL LOW" */;

// Verilog 2001

(* altera_attribute = "-name POWER_UP_LEVEL LOW" *) reg Enable_3V;

as well as

reg Enable_3V = 1'b0;

but none of them works.

between power on and until the fpga starts to work in user mode the pin is 1

as soon as the user mode is reached, this pin goes to 0

so it seems that it is realy impossible ...

i can't go to 2k pull down as this will disable the soft start function of the dcdc

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