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Altera_Forum
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17 years ago

Cyclone3 Power Up level doesn't work

A design with an EP3C40F324I7 has the pin U18 as an registered output. This pin is used to control another dcdc's nSHDN (Shutdown negativ logic) The fpga is configured via epcs. this dcdc is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

yes thats true FvM, thats what i had done now.

i looked into the datasheets again and with the following conditions that must be met

Vio FPGA 3,0V

Voff nSHDN < 0,4V

Von nSHDN >2,5V

i changed the resistors to 180 and 1100 Ohm

So i get 0,39V and 2,57V @ nSHDN

The C will be something between 1 - 10uF depending on availability

the divider with 180 and 1100 ohm will have current of ~2mA @ 3,0Vio

what if i set currrent strength to 2mA for that pin,

would that have a negative side effect or could this limited slew rate help ?

EDIT : Current Strength minimum is 4mA