Forum Discussion
Altera_Forum
Honored Contributor
8 years agoThe data stream could be erroring. In which case you'd see nSTATUS going off early. You can calculate how long it should take to configure given the image size, configuration clock speed and config data width. If nSTATUS goes off before it's finished you have an error.
I'd also question the integrity of the power rails. Is something else switching on whilst the FPGA is configuring, causing one of the rails the FPGA depends on to dip? This might cause the FPGA's configuration state machine to reset and start again. Is something happening 175ms in, when you said nSTATUS is asserted low? If this was still happening having reduced the configuration clock speed it would indicate it's not necessarily FPGA related. Cheers, Alex