Forum Discussion
Altera_Forum
Honored Contributor
8 years agookay, I have tried it with the clock speed set to 12.5 MHz. The DCLK frequency is now 9.8 MHz.
It still doesn't configure. As I understand it, the FPGA must be reading at least some of the configuration data, otherwise it wouldn't have kept the clock rate at the lowest setting. Is there any way to establish how far it gets before a problem occurs? Rod