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Honored Contributor
8 years agoI'm concerned you have a signal integrity issue. Everything you're doing is correct. Are you confident it'll run at 80MHz? nSTATUS (and nCONFIG?) being asserted every 175ms is consistent with it restarting - in x4 mode at 80MHz your device should have completely configured in that time. So, this seems to be a new attempt being made by the FPGA to configure.
You could monitor nSTATUS. If this ever goes low during delivery of the configuration data it indicates an error. (Note: nSTATUS also follows nCONFIG low at the start of the configuration cycle.) Try slowing the configuration clock (DCLK) frequency - reduce it to minimum. "altera enhanced configuration devices (https://www.altera.com/en_us/pdfs/literature/hb/cfg/ch_14_vol_2.pdf)" discusses this and shows how this is done. Cheers, Alex