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I am trying to use subLVDS I/O on the SOC cyclone dev kit. I have a camera with DDR2 outputs, do I need to wire the data and clocks to the transceiver ports on the FPGA, or can I just use a macrocell configuration on any differential pins (that support sub-LVDS)? I am not getting sensible data from the camera as yet when I use bank 8A for the subLVDS data and clk inputs.
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Hi,
I use DIFFIO_RX sub_LVDS input of bank 4A for the serial data input and CLK3P/N of the clock input of that bank also sub_LVDS (DDR). That works nicely. You have to take care of impedance matching and a good cable or other connection.
To convert the serial data stream to parallel data, ALTLVDS_RX function is used.
Hope this helps.
Honored Contributor
