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Altera_Forum
Honored Contributor
10 years agoI am trying to use subLVDS I/O on the SOC cyclone dev kit. I have a camera with DDR2 outputs, do I need to wire the data and clocks to the transceiver ports on the FPGA, or can I just use a macrocell configuration on any differential pins (that support sub-LVDS)? I am not getting sensible data from the camera as yet when I use bank 8A for the subLVDS data and clk inputs.