Cyclone V SX SoC - DMA Controller Peripheral Request Interface

Dear BadOmen

As per my understanding of the verilog code, I think that your explanation of the RX and TX interfaces is mixed up. It should be the other way round. Am I correct?

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Those are the DMA "peripheral request interface" signals. The RX group is for flow control of receive channel of the FIFO (writing data to the FIFO) and the TX group is for the flow control of the transmit channel of the FIFO (reading data from the FIFO).

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I think the RX and TX here are in terms of the DMAC. It uses the TX channel to write data to the FIFO and RX channel to read the data from the FIFO.

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tx_single represents the FIFO not full status

rx_single represents the FIFO not empty status

tx_burst represents the FIFO having a fill level equal to or exceeding the burst size

rx_burst represents the FIFO having a fill level low enough that it can handle another burst of data written into it

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Again here the single and burst signals contradict each other. Only looking at the single signals, FIFO not being full implies that tx channel is used for writing into the FIFO and not empty implies that rx channel is used for reading from the FIFO.

Sincerely

Ankit