Cyclone V SX SoC - DMA Controller Peripheral Request Interface

Those are the DMA "peripheral request interface" signals. The RX group is for flow control of receive channel of the FIFO (writing data to the FIFO) and the TX group is for the flow control of the transmit channel of the FIFO (reading data from the FIFO).

tx_single represents the FIFO not full status

rx_single represents the FIFO not empty status

tx_burst represents the FIFO having a fill level equal to or exceeding the burst size

rx_burst represents the FIFO having a fill level low enough that it can handle another burst of data written into it

rx_ack is a signal that pulses every time the DMA either issues a flush or acknowledges a peripheral transfer

tx_ack .... same thing for the TX channel

When I say "burst" in this context I'm talking about a predefined block of data and not memory-mapped bursts. The burst size programmed into the peripheral needs to match the burst size programmed into the DMA channel thread. These PRI interfaces let the peripherals communicate to the DMA letting it know when it's safe to transfer data. I recommend reading the DMA chapter of the technical reference manual as well as the comments in the custom FIFO IP to learn more about peripheral transfers and how the handshake works. This group of single, burst, and acknowledge signals is defined by Synopsys and used within the HPS block for all the Synopsys IP that communicates with the DMA-330 core.