Honored Contributor
Honored ContributorDear BadOmen
A question about the design: In the component editor of the Loopback FIFO (our flow control fifo), for tx_single/burst/ack and rx_single/burst/ack signals I see that although the signal types are export, the interfaces are tx_pri and rx_pri. How do I get this? What are these *pri interfaces? In my design there is a catch. I have to create a peripheral in which there are 2 fifos and some processing logic in between the 2. As per my understanding I will have to use fifos that have Avalon Slave MM write interface and Avalon Slave ST source interface for the input fifo and Avalon Slave ST sink interface and Avalon Slave MM read interface for the output fifo. I know that I can instantiate these fifos directly from the IP catalog, and when I generate the design, the verilog files will be automatically created. My question is that how do I add the wrapping flow control logic that you have used in the flow control fifo design example? Thank you for being so patient with me and helping me with this design project. I go to school and I lack the wisdom that you and all the other people have on this forum. Sincerely Ankit
