Cyclone V SX SoC - DMA Controller Peripheral Request Interface

I didn't realize the hardware was posted but I took a look and it contains the necessary verilog and .tcl file under /ip/flow_control_fifo. If you try to use that FIFO in your own design just move the IP directory to your own hardware project and the flow control FIFO will show up the next time you open Qsys. That design is just an old version of the golden hardware reference design with the FIFO added to the system and some wiring of the DMA flow control signals at the top level.