Cyclone V SX SoC - DMA Controller Peripheral Request Interface

Dear BadOmen

Referring to your flow_control_fifo.v file. I am having trouble instantiating and integrating that component in Qsys. As per my understanding the data port and the tx+rx ports are connected to the DMAC; the csr port is connected to the hps. When I create a new component in Qsys, the data and csr ports from the verilog file are automatically detected as interfaces with correct signal types. However I am not sure what to do with tx and rx ports of the verilog file? Which interface would they be a part of and what would the signal type be? Should I make them conduit_end and export the signals? In that case how would I connect them to the DMAC at the SoCKit top level file.

In short, would you have an example project with this fifo implemented as a peripheral?

With regard to you reply above, again, can you please share some design project so that I can learn and modify it as per my needs.

Sincerely

Ankit