Cyclone V SX SoC - DMA Controller Peripheral Request Interface

Thanks for you Reply,

so this flow control fifo example and the fpga_dma example driver from altera just use DMA Controlled Length Management? Hard to understand the driver :/.

I thought I can give the length information with the DMA Request Interface. Like the fpga logic push a request with length information inside.

So either the DMA Controller has to read every time I want to use a peripheral request(with different packet size) the register of my fpga logic (DMA Controlled Length Managemengt )OR

the length information can be attached to the request (Peripheral Length Management).

In my case I receive Packets with different size via Avalon Streaming and want to give the information with the peripheral request, and not that the DMA Controller has to read every time the length register of my fpga logic. I would understand the documentation of altera that both scenarios are possible, but the FPGA peripheral requist interface is different compared to the interface inside the HPS logic.

I hope my english is understandable ;) . Thanks a lot badOmen

I would understand your post like I have to agree the length before the peripheral request occour?