Cyclone V SoC Dev Kit PCIe End Port Example

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Hi Angad,

You mean you just want to see if the wires on the PCIe connector are working? If the root-complex is an FPGA, then sure, you can do whatever you like.

For example, you can test a high-speed transceiver by configuring it in BIST mode and have it generate a PRBS pattern, or you can use a transceiver IP core and configure it manually and have it output a desired pattern. For example, a square wave at a low enough frequency that you can see it on a scope. You can also loop back the TX and RX differential signals using a PCIe breakout cable (Samtec sell them).

http://www.samtec.com/technical-specifications/default.aspx?seriesmaster=pcrf

I use this type of cable (the one with the peripheral style connector) as a way to access transceivers on kits that do not have HSMC or FMC connectors.

Cheers,

Dave

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Hi Dave,

Thanks for the quick response.

I am testing the following design: http://rocketboards.org/foswiki/view/projects/pcierootportwithmsi

If you Look into "Open Issue" - FB 165881 – Kernel can’t boot up if don’t have end point

I have applied the patch that they are giving. It works fine on the Dev kit, But I tried the same patch for Other Cyclone V Device(5CSXFC6C6U23I7ES) The patch seems to fail.

Basically from the patch I understood that the RootPort is being forced to complete the Enumeration But I dont understand why it wont work for other device other than Dev kit.

Regards

Angad