Forum Discussion
DBart1
New Contributor
New ContributorCyclone V Resource Property Editor Questions
I have having difficulty understanding the chip planner resource property editor view of the ALM in a Cyclone V . I have read the Cyclone V handbook section on the LAB/ALMs but that does not seem to...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi DBart1,
Here is the FPGA Architecture White Paper for your reference:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01003.pdf
The masks reflects the hardware format which has active low data inputs rather than the logical view you see in Resource Property Editor.
Thanks.
