Cyclone V PLL reconfiguration don't work

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Hello,

I tried to utilize one of the examples of the AN-661 (Implementing Fractional PLL Reconfiguration with

Altera PLL and Altera PLL Reconfig IP Cores) to reconfigure my PLL dynamically. The example is "PLL Reconfiguration with Altera PLL Reconfig IP Core to Reconfigure M, N,

and C Counters". I just utilized the state machine of the example and I created a new design because the example its for the Stratix V.

So, i write all comands necessarys and I read the confirmation that the reconfiguration its done, but the output frequency doesn't change.

I really hope you can help me or give me a hint who could help me, because I really despair of that problem.

thanks for your time,

Jorge

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Hi, I'm tony stark, but i am not a Iron man today, wish to ask you ,did you try to simulate this in hand before ?

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You can try to simulate your reconfiguration steps in Modelsim to see if thing goes as expected. It would be easier to debug in simulation.

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Thanks for your reply.

I'm already doing the simulation. Indeed, I'm thinking about if the problem could be the simulation. Do you know if there is any connexion ?

Jorge

Thanks for your reply, bfkstimchan.

The target device is the Stratix V. Ok , i will take a look about it.

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Thanks for your reply.

I'm already doing the simulation. Indeed, I'm thinking about if the problem could be the simulation. Do you know if there is any connexion ?

Jorge

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Is it that you are observing similar issue in Modelsim simulation?

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Thanks for your reply, bfkstimchan.

The target device is the Stratix V. Ok , i will take a look about it.

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so did you get it working already by now?