Forum Discussion

TMayd's avatar
TMayd
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone V PLL Clock switchover Timing Constraints

Hello! I've implemented a design with the altera PLL using the clock switchover, specifically auto switch with manual override. I have logic on my system base clock that determines if an incoming...
TMayd's avatar
TMayd
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello,

The above answers does "solve" the problem but I'd like to know if this is the proper way to constrain the design per Intel? I'd also like feedback from intel as to why "derive_pll_clocks" does not work for the PLL using clock switchover?

Tyler