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TMayd's avatar
TMayd
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone V PLL Clock switchover Timing Constraints

Hello! I've implemented a design with the altera PLL using the clock switchover, specifically auto switch with manual override. I have logic on my system base clock that determines if an incoming...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

Perhaps you need to use the -create_base_clocks option when you do this.

The "5V" was confusing because we're talking about time, not voltage. In general, you do not want to have the same value for both -max and -min with set_output_delay. -max is for meeting setup timing and -min is for meeting hold timing.

TMayd's avatar
TMayd
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

I did have that option checked. I even tried deleting the base clocks, rerunning, but still got the same issues. At this point I'm closing timing and everything is checking out on my peripherals by manually defining the clocks. I just thought (hoped) that there was a cleaner /easier way to accomplish it.

I appreciate you taking the time and the advice! Typically I agree regarding the delay, but in this case the data sheet listed the same value for both setup and hold. ¯\_(ツ)_/¯

Thanks for responding to me. Cheers!