Forum Discussion
TMayd
Occasional Contributor
Occasional ContributorCyclone V PLL Clock switchover Timing Constraints
Hello!
I've implemented a design with the altera PLL using the clock switchover, specifically auto switch with manual override. I have logic on my system base clock that determines if an incoming...
sstrell
Super Contributor
Super ContributorPerhaps you need to use the -create_base_clocks option when you do this.
The "5V" was confusing because we're talking about time, not voltage. In general, you do not want to have the same value for both -max and -min with set_output_delay. -max is for meeting setup timing and -min is for meeting hold timing.
