Occasional Contributor
Super ContributorSorry, I forgot that the switchover feature can be part of the PLL itself instead of requiring the clock control block in front of it. I'm surprised derive_pll_clocks doesn't work with this. What does the "Report clocks" command in the timing analyzer show when you use derive_pll_clocks?
You have a typo in your first set_output_delay (double underscore). And what clock is dac_ld_sclk_int in the 4th one?
You're also missing -max and -min for your set_output_delay constraints. But you say max and min are the same at 5 V (?). Not sure if these are all typos.
Occasional ContributorI was also surprised. I believe the issue is that it is looking for a master clock to derive the generated clock. I don't really understand why it won't make the timing paths for both as they are mutually exclusive.
Specifically the timing analyzer throws "The base clock assignment for generated clock pll_inst|pll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] cannot be derived"
When I run report clocks it shows the issue:
"The master clock for this clock assignment could not be derived. Clock: pll_inst|asec_pll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] was not created."
"Clock: MCLK40M found as a potential master clock candidate"
"Clock: clk_in found as a potential master clock candidate"
Digging into the PLL it seems that the derive PLL clocks command usually derives the base clock at the VCO and then generates the rest of the clocks off of this generated clock.
Sorry I was trying to match my diagram quickly. I have quite a few more signals in my full design so I was just trying to simplify it. Those typos don't really exist in the true SDC file which is much longer. (dac_ld_sclk_int is the real signal).
I believe omitting -max and -min is the same as indicating -both, since the setup and hold times are same value per my device data sheet (at 5V, sorry again the comment was to remind future-me of why they're the same).
