Occasional Contributor
Super ContributorFirst of all, set_input_delay and set_output_delay should be referencing virtual clocks, the clocks that drive your connected devices (I call them upstream for input devices and downstream for devices fed by the FPGA). I don't see virtual clocks in your .sdc unless those are supposed to be your "clk_in" and "clk_out", in which case they should not have targets in the constraints.
And when you say "clock switchover", are you saying you are using a clock control block to switch what clock is going into the PLL? Maybe a little diagram or better explanation of your clock network would be helpful.
Occasional ContributorThanks for your comments and reply!
I've attached a picture that I hope will clarify what I'm trying to accomplish. I've attached a simplified SDC of how I believe I should be constraining the design. Since the clock driving the off-board dac originates from the FPGA I figured I should use a generated clock and not a virtual clock.
For clock switchover I have implemented the cyclone V PLL (http://www.altera.com/literature/ug/altera_pll.pdf) with the Automatic
Switchover with Manual Override. I have two incoming clocks and if "clk_in" is present and stable (determined by the clkbad port from the PLL) I want the device to switch to that clock, from the clock MCLK40M.
Both clocks are connected to clock pins on the FPGA so I am unclear as to why I would need to use the clock control block before wiring in the PLL. If this is the correct practice I'll happily comply.
