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ESaiv's avatar
ESaiv
Icon for New Contributor rankNew Contributor
4 years ago

Cyclone V Passive Serial configuration failing after many bits.

Hello. I am attempting to configure my Cyclone V SoC FPGA using passive serial (PS) configuration on a custom PCB. Sometimes, my configuration fails at the 1st bit; other times, it fails after someth...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

The error might be caused by the following issue. Can you please check?


  • Incorrect device selected
  • User start up clock selected but no running clock connected to CLK_USR pin
  • Communications cables not securely connected
  • No power to target system


ACTION: Make sure all cables are securely connected, select a different device, check the power on the target system.Make sure you have connected a start-up clock for initialization of the CLKUSR pin, or specify that the device not use a user-supplied clock on the CLKUSR pin for initialization.


  • ESaiv's avatar
    ESaiv
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello,

    Thanks for the response. I ensured each of those things were done. I fixed my issue by re-floating a few pull-up resistors on important pins such as nSTATUS, nCONFIG, etc. All works well now.