Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Cyclone V Native Transceiver CDR vs. Refclk PPM Detector

Hello, I am implementing the SATA protocol on a Cyclone V FPGA. So far I have everything working with an older (SATA GEN 1) device, but to move to a newer device, I need a way to determine if t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

As a quick follow up to this, I noticed that one can also export rx_pma_clkout from the Native Transceiver. According to the user guide, rx_pma_clkout: is" the RX parallel clockwhich is recovered from the serial received data is anoutput of the PMA", and seems like it maybe is the clock that should be monitored to check if the CDR is locked to data at the right speed?

When checking this with signal tap, however, I didn't see this change with variable data speed, it just looked like rx_clkout multiplied by the serialization factor.

Any tips?