Hello, I'm trying to figure out how large a design I can implement in a Cyclone V FPGA. It's widely documented that the device can accommodate 110K LEs. But what's an LE? An inverter? A basic gate? A F/F? A 256 bit shift reg? TIA for any guidance on this. A spec of some kind on the subject would be really helpful. Again, thanks, Bill McDonald

Hello Bill,I assume the article FPGAs: System gates or logic cells/elements? can be helpful: www.eetimes.com/fpgas-system-gates-or-logic-cells-elementsA fragment from the mentioned article:"Each LUT could be used to represent a function that would be the equivalent to some number of equivalent gates. For example, someone once told me that a 4-input LUT could be used to represent functions that were the equivalent of anywhere between 1 and 20+ regular logic gates." I would recommend to try to implement your project in the Quartus design system for Intel/Altera Cyclone V family. This device family is supported via free Intel Quartus Prime Lite Edition. (https://fpgasoftware.intel.com/?edition=lite). Regards,Martin

Hi Bill You can refer to definition here: https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/reference/glossary/def_logelem.htm Thanks. Eng Wei

Hi BillHope your issue is resolved. I am transitioning this thread for community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.Eng Wei

Hi Martin, Sounds like exactly what I'm looking for; I'll definately check it out. Many thanks, Bill

Hi Eng Wei, Many thanks. This is very helpful and nicely supplements the information previously sent by Martin. Best, Bill

Cyclone V Logic Elements | Altera Community

5 Replies

MBenca
Occasional Contributor
4 years ago

Hello Bill,
I assume the article FPGAs: System gates or logic cells/elements? can be helpful: www.eetimes.com/fpgas-system-gates-or-logic-cells-elements
A fragment from the mentioned article:
"Each LUT could be used to represent a function that would be the equivalent to some number of equivalent gates. For example, someone once told me that a 4-input LUT could be used to represent functions that were the equivalent of anywhere between 1 and 20+ regular logic gates."

I would recommend to try to implement your project in the Quartus design system for Intel/Altera Cyclone V family. This device family is supported via free Intel Quartus Prime Lite Edition. (https://fpgasoftware.intel.com/?edition=lite).

Regards,
Martin
- BillM256
  Occasional Contributor
  4 years ago
  Hi Martin,
  
  Sounds like exactly what I'm looking for; I'll definately check it out.
  
  Many thanks,
  
  Bill
  - EngWei_O_Intel
    Frequent Contributor
    4 years ago
    Hi Bill
    
    You can refer to definition here:
    
    https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/reference/glossary/def_logelem.htm
    
    Thanks.
    
    Eng Wei
EngWei_O_Intel
Frequent Contributor
4 years ago
Hi Bill

Hope your issue is resolved. I am transitioning this thread for community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei

Forum Discussion

Cyclone V Logic Elements

5 Replies

Recent Discussions

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger

Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Can you Validate MAX10 Date and Lot Code?

Part Status request

Agilex 7 Decoupling capacitor scaling factor