Forum Discussion
7 Replies
- Kshitij_Intel
Frequent Contributor
Hi,
I will check on your questions and get back to you.
Thank you,
Kshitij Goel
- SDavi9
Occasional Contributor
Dear K**bleep**ij,
If it is supported does Intel have any Documenation on this ?
What about a Quartus design e.g. ?
Thank you for all your help once again
Bests regards
Shmuel
- Kshitij_Intel
Frequent Contributor
Hi,
Let me follow up on this with the team.
Thank you,
Kshitij Goel
- SDavi9
Occasional Contributor
Any News ?
- Kshitij_Intel
Frequent Contributor
Hi,
Support speed range of Cyclone V GX(622Mbps ~ 3.125Gbps) / GT (622Mbps ~ 5.0Gbps).
For #1, Minimum bit rate is 622MHz (max run length is 200 UI). You can refer to CV Datasheet.
For #2, It should be totally balanced. I don't know exact allowable running disparity characteristics, but it should be within +/- 2or3 (<8B10B). You can find the limit by the web search like below.
For #3, Maybe it is AC-coupled configuration, so data toggling is needed to keep balannced signal. Same as #2 it should be DC-balance signal needed for AC-coupling.
Hope this will clarify.
Thank you,
Kshitij Goel
- SDavi9
Occasional Contributor
Dear K**bleep**ij Goel,
Do you have any design examples that could test this on a Cyclone V GT development board ? We specifically need a design that will enable us to transmit \ receive between a NIOS and an external optical transceiver ?
Best regards
Shmuel
- Kshitij_Intel
Frequent Contributor
Hi,
As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you,
Kshitij Goel