Forum Discussion
Occasional ContributorCyclone V GX, Custom PHY, using fPLL as TX PLL
Okay, I have a valid PLL configuration now: two fPLLs that feed as external PLLs into three transceivers each.
For reference: the fPLL's output port is not valid as an input clock for a transceiver block if reconfiguration is enabled, because that routes the clock through the per-output C divider to allow reconfiguration to set up a divisor here, this gives an error message that the CLKCDRLOC port on the transceiver is not properly connected. The knowledge base entry for this is incomplete: connecting to outclk_0 only works if PLL reconfiguration is disabled.
The solution here is to disable reconfiguration for the fPLLs, or enable access to the DPA outputs in the PLL configuration and connect the clock to phout[0], then the design compiles.
Occasional ContributorHi,
okay, I'm still trying to wrap my head around this.
Table 2-4 in CV-53002 mentions an x1_fPLL line that goes to three channels each (so I'd have to run both fPLLs with identical settings), and table 2-6 mentions a path for bonded configurations
fPLL » x1_fPLL » central clock divider » x6 » individual clock divider » serializer
Both of these sound like I can feed the x1_fPLL line directly into the channel divider, which would free the channel PLL for CDR. Since I don't need bonding mode, I can skip the step where the divider output is then fed back into the x6 network. Each group of three is then limited by the slowest device, but that is probably not a problem in practice.
I can see that this isn't possible with the Custom PHY, would it help to switch to Native PHY?
Regarding the clock source for the fPLL, table 2-1 answers my question -- the routing I had in mind would be very jittery, so I'll feed in a high-speed clock via GXB_REFCLK.
Simon
Occasional ContributorOkay, I have a valid PLL configuration now: two fPLLs that feed as external PLLs into three transceivers each.
For reference: the fPLL's output port is not valid as an input clock for a transceiver block if reconfiguration is enabled, because that routes the clock through the per-output C divider to allow reconfiguration to set up a divisor here, this gives an error message that the CLKCDRLOC port on the transceiver is not properly connected. The knowledge base entry for this is incomplete: connecting to outclk_0 only works if PLL reconfiguration is disabled.
The solution here is to disable reconfiguration for the fPLLs, or enable access to the DPA outputs in the PLL configuration and connect the clock to phout[0], then the design compiles.
