Cyclone V GX, Custom PHY, using fPLL as TX PLL

Okay, I have a valid PLL configuration now: two fPLLs that feed as external PLLs into three transceivers each.

For reference: the fPLL's output port is not valid as an input clock for a transceiver block if reconfiguration is enabled, because that routes the clock through the per-output C divider to allow reconfiguration to set up a divisor here, this gives an error message that the CLKCDRLOC port on the transceiver is not properly connected. The knowledge base entry for this is incomplete: connecting to outclk_0 only works if PLL reconfiguration is disabled.

The solution here is to disable reconfiguration for the fPLLs, or enable access to the DPA outputs in the PLL configuration and connect the clock to phout[0], then the design compiles.