Forum Discussion
Occasional ContributorCyclone V GX, Custom PHY, using fPLL as TX PLL
Okay, I have a valid PLL configuration now: two fPLLs that feed as external PLLs into three transceivers each.
For reference: the fPLL's output port is not valid as an input clock for a transceiver block if reconfiguration is enabled, because that routes the clock through the per-output C divider to allow reconfiguration to set up a divisor here, this gives an error message that the CLKCDRLOC port on the transceiver is not properly connected. The knowledge base entry for this is incomplete: connecting to outclk_0 only works if PLL reconfiguration is disabled.
The solution here is to disable reconfiguration for the fPLLs, or enable access to the DPA outputs in the PLL configuration and connect the clock to phout[0], then the design compiles.
Regular ContributorHI,
Your understanding of fPLL clocking capability is correct in the sense that we should be able to use fPLL to clock multiple transceiver channel using xN clock network.
Custom PHY is tied up with limitation of using CMU PLL only
For NativePHY, we have option to enable "use external Tx PLL"
- With this setting enable, it will expose one clocking port that we can connect to external fPLL IP
Feel free to test it out.
Thanks.
Regards,
dlim
Occasional ContributorHi,
that sounds like what I need.
I've investigated a bit, and if I read the SystemVerilog code right, it will unconditionally create a TX PLL per channel even in "external PLL" mode (the respective section is instantiated every time the TX path is enabled).
Is this generated PLL supposed to be merged with an existing fPLL instance, or is it supposed to be removed as the clock selection mux instantiated behind it removes its fanout?
The clock ports seem to be named, and .clkffpll is mentioned twice in altera/altera_xcvr_generic/cv/cv_tx_pma_ch.sv:
altera/altera_xcvr_generic/cv/cv_tx_pma_ch.sv:233:// .clkffpll (wire_clk[3] ), altera/altera_xcvr_generic/cv/cv_tx_pma_ch.sv:268: .clkffpll (1'b0/*TODO*/ ),
One of these is a comment, and the other one is a hardcoded zero in a "synopsys translate_off" block, so it seems I cannot connect anything to this port, which would explain why I get an error message if I instantiate the Native Transceiver PHY with a PLL count of 4 and select PLL 3 as the main PLL (which would translate to
pll_sel = 3
and therefore to
tx_cgb.x1_clock_source_sel = "ffpll"
I'll investigate further, but it seems to me that I need to skip the MegaWizard here, and instantiate the components directly, is that correct?
Simon
