Cyclone V differential HSSI REFCLK implementation

Hello,

I am trying to use a differential clock input of REFCLK pins for an HSSI interface on a Cyclone V FPGA. I have tried passing the differential clock inputs through an ALTIOBUF to get a single ended clock to use to clock the data from the transceiver Phy, but I get the following errors:

Error (177035): The input pin adc_dco_p[0] assigned to HSSI Pin_AA11 has no fanout.

Error (177035): The input pin adc_dco_n[0] assigned to HSSI Pin_AB10 has no fanout.

Info (171121): Fitter preparation operations ending: elapsed time is 00:00:46

Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

Error (171000): Can't fit design in device

Here is the VHDL code for the ALTIOBUF:

altiobuf_adc_dco : altiobuf_1

PORT map

(

datain => adc_dco_p,

datain_b => adc_dco_n,

dataout => adc_dco

);

I am trying to use the adc_dco output to clock a register or I would like to input the differential clock to a PLL.

What is the correct way to implement the differential clock inputs to HSSI REFCLK pins to use for clocking the transceiver phy data?

Thanks.