New Contributor
Super ContributorHi,
4-1. Setting AS Interface and User I/O Interface:
For AS Interface, the default settings are fine. And the Tool automatically connects to the AS Interface without the need to explicitly connect to the FPGA external PIN.
If you're using EPCQ flash, can just use the AS (Active Serial) Interface with default settings where "Disable dedicated AS interface" and "Enable SPI Interface" boxes can be left unchecked. Then set the MSEL pins of the FPGA devices to the AS configuration mode.
"Disable dedicated AS interface" and "Enable SPI Interface" only enabled when want to access the general purpose QSPI flash (user I/O) or for Intel® MAX® 10 devices.
Design examples:
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
New ContributorSorry for the late reply, I have been unable to login for some time.
"Disable dedicated AS interface" and "Enable SPI Interface" only enabled when want to access the general purpose QSPI flash (user I/O) or for Intel® MAX® 10 devices.
I am taking that to mean these settings can be left unchecked because I am on a Cyclone V?
So I have my Generic Serial Flash Interface with outputs to internal signals that just terminate in the file that instantiates them? I believe I have tried that but the fitter does not route them to the dedicated I/O pads.
Maybe I am forced to use Platform Designer with the Nios processor to make this work?
Super ContributorYa those settings can be left unchecked if you're using EPCQ flash since not need to explicitly connect to the FPGA external PIN.
May be you can try to use Platform Designer with the Nios processor and refer to the document steps.
