New Contributor
Super ContributorHi,
I further found something in the link below under 4-1. Setting AS Interface and User I/O Interface:
Connection with GSFI Flash ROM supports both AS (Active Serial) Interface and User I/O.
For AS Interface, the default settings are fine. And the Tool automatically connects to the AS Interface without the need to explicitly connect to the FPGA external PIN.
For User I/O, enable the "Disable dedicated Active Serial interface" and "Enable SPI pins interface" settings as shown in [Fig.4]. Export the signal that connects to the Flash ROM and connect directly to the FPGA external PIN that connects to the Flash ROM. Also, do not forget to write the timing constraint file (SDC file).
Nios ® II Boot Option ~ EPCQ Flash ~ (using AS IF)
Nios ® II Boot Option ~ QSPI Flash ~ (using User I/O IF)
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
New ContributorThank you for your information. We are in fact foregoing a soft processor and making these Flash writes ourselves. I do have these settings for the Configuration type to be AS x4, the "Disable dedicated AS interface" and "Enable SPI Interface" boxes are checked, the signals are routed from the IP to their top level ports, and these ports have been assigned to the appropriate pins. I only have the option to set the drive strength to maximum, minimum, and 2mA. The Slew rate defaults to 1 (fastest). Could this be an issue with the target platform of Cyclone V?
