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Altera_Forum
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8 years ago

Cyclone V DDR3 package deskew

Dear folks, I'm currently designing a Cyclone V DDR3 Ram interface with a single component DDR3L using the hard memory controller. In EMIF handbook I find, that for clock < 933MHz no package de...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi Andreas,

Yes, it is true that some package length is more than 100ps. Anyway, do not worry on that. Quartus timequest will make the timing analysis based on the package length. What user have to achieve is to meet the 20ps on the board trace matching. Enter those board parameters into GUI , generate the IP and see it the full compilation close timing.

For more information, Cyclone V UniPHY do not support package deskew. What user have to achieve is to meet the board design guideline and let quartus handle the package skew different in timing analysis.

Hope this helps.

(This message was posted on behalf of Intel Corporation)