Forum Discussion
EdJ
New Contributor
4 years agoSorry, it was somebody else that asked the question 7 years ago. I located it when I searched the forum before I posted. The reason for the option in Quartus to force I/O voltages in the bank to be consistent with VCCPGM was not made clear in the responses to that question. That question as well as mine referred to the Cyclone V series. After posting I realized that other chips supported by Quartus may require that the I/O in the config bank must have the same voltage as the programming voltage, so that is why the box option is there.
While I have your attention, could you confirm that my scheme and voltage choices (JTAG voltage, JTAG pull-up voltage, config pin pull-up voltage, I/O bank 3A voltage) described in my 1st post are correct for ASx4, with config device programming via the Serial Flash Loader? Thanks a lot.
Ed
While I have your attention, could you confirm that my scheme and voltage choices (JTAG voltage, JTAG pull-up voltage, config pin pull-up voltage, I/O bank 3A voltage) described in my 1st post are correct for ASx4, with config device programming via the Serial Flash Loader? Thanks a lot.
Ed
AminT_Intel
Regular Contributor
4 years agoHello,
I think your scheme and voltage choice looks good so far. You can refer to Pin Connection Guidelines for more details on power supply: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf
Thank you.
- AminT_Intel4 years ago
Regular Contributor
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.