Cyclone V Clock Not Toggling

I've tried both. I originally tapped the DRAM signals with the outputted clock which is a PLL(ref clock is CLK5p) output. But, since that outputted clock was not toggling I tried using the input clock directly and I received the same results. I recently connected another clock (CLK10p, references programmable clock X4) which caused the outputted DRAM clock to toggle. However, I cannot write to the DRAM because the bus waitrequest indicates that its busy. I have tried resetting as well as attempting to write to the bus even though waitrequest indicated busy. Those both did not allow any valid writes or reads and did not toggle the bus wait request.