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Altera_Forum
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9 years ago

Cyclone-V changing off-chip signal timing using IObuf delays

Because of routing differences in a bus system we want to experiment with input IO-buf delays of a cyclone. The D3_delay and D1_delay options in the quartus assignment editor are available but...
Altera_Forum's avatar
Altera_Forum
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9 years ago

You should use Fast I/O register assignment before resorting to buffer delays (which without looking at the document I think are usually in 50 ps increments). That makes the design use the input or output register located in the I/O block, the closest it can be to the I/O pin.