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Honored Contributor
Honored ContributorCyclone V bidirectional half-duplex LVDS?
Dear All, We are designing a board with a Cyclone V connected to another (already existing) board via a bidirectional half-duplex LVDS link. We would prefer to use only 2 pins of the FPGA to im...
Altera_ForumHonored Contributor
Honored ContributorThank you a_x_h_75!
We are happy that it is correct. However, I am not sure to understand the AN522 "Implementing Bus LVDS Interface in Supported Altera Device Families", on page 6, there is a footnote "DIFFIO_TX pin does not support true LVDS differential receivers". Does it mean that for our purpose one should *not* use DIFFIO_TX pins, but DIFFIO_RX pins work well (can be transmit/receive/be tri-stated). Indeed Quartus selected some DIFFIO_RX pins. Nevertheless it seems that our goal is somehow similar to Bus-LVDS?
