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The inversion. You are supposed to pass data as it is. Inverting first bit introduces error naturally. Inverting msb converts to offset binary. You haven't explained clearly why you think you need to invert it.
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Sending 0101 and measuring (in hardware, with a scope) 1101 should be a fairly clear indication that something is wrong. That the design works fine when I manually invert the first bit of each stream in the parallel data also seems to be a reasonable indication that I'm not just dreaming that something is strange. That said, a simplified design does not show this behaviour in an RTL simulation. My attempt to also perform a timing simulation failed with "Warning (10905): Generated the EDA functional simulation files although EDA timing simulation option is chosen.", which probably means that this is not supported with my Quartus II license. I might download this simple design to some hardware and measure the signals when I get my hands on a fast scope again.
It's good anyway to know that this is not the supposed behaviour. Thanks for that.
Regards,
Philipp
Honored Contributor
