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All data lines come from the same dedicated SERDES hardware. The clock is generated by another of those channels with a fixed pattern of 0101. TimeQuest reports a maximum skew (TCCS) between all those lines of 250ps, so the delay between any data line and the clock line is at most 250ps, which is fine for the DAC's setup/hold requirements (the clock is delayed in the DAC to get a positive hold time). Maybe I could add explicit constraints to compensate for some trace lengths, but at least at the moment this is not necessary.
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If DAC only has skew requirement then you still need to control that (from build to build) using set_output_delay with the required skew.
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Do you mean my answer or the described behaviour? The latter doesn't make any sense to me either, that's why I'm looking for an explanation.
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The inversion. You are supposed to pass data as it is. Inverting first bit introduces error naturally. Inverting msb converts to offset binary. You haven't explained clearly why you think you need to invert it.
Honored Contributor
